華閱文章網VHDL 元件例化語句
引用的東西要在同一個project里的其他文件里有定義才行。
給你個例子看下就明白了，這是引用一位全加器構成一個四位全加器。
project名是adder，里面兩個vhd文件，分別為*和*
*內容如下：
LIBRARY IEEE;
USE *_LOGIC_*;
USE *_LOGIC_*;
USE *_LOGIC_*;
ENTITY FullAdder is --這是一位全加器
port(
A:in std_logic;
B:in std_logic;
C:in std_logic;
Carry:out std_logic;
Sum:out std_logic
);
END FullAdder;
architecture a of FullAdder is
begin
SumCarryend a;
*內容如下：
LIBRARY IEEE;
USE *_LOGIC_*;
USE *_LOGIC_*;
USE *_LOGIC_*;
entity adder is --四位全加器
port(
A,B:in std_logic_vector(3 downto 0);
S:out std_logic_vector(3 downto 0);
C:inout std_logic_vector(4 downto 0)
);
end adder;
architecture a of adder is
component FullAdder --聲明component
port(
A:in std_logic;
B:in std_logic;
C:in std_logic;
Carry:out std_logic;
Sum:out std_logic
);
end component;
begin
u1:FullAdder port map(A(0),B(0),C(0),C(1),S(0));
--引用component,u1,u2,u3,u4為映像的標識名，port map是關鍵字，端口按對應順序寫
u2:FullAdder port map(A(1),B(1),C(1),C(2),S(1));
u3:FullAdder port map(A(2),B(2),C(2),C(3),S(2));
u4:FullAdder port map(A(3),B(3),C(3),C(4),S(3));
C(0)end a;
VHDL元件例化語句報錯問題
接口映射不應該放在進程里面，改為下面代碼試試：begin。
.u0:text101 port map(clk,reset,outclk1);process(reset,clk) begin if reset = '1' then current_state <= s0; elsif rising_edge(outclk1) then current_state <= next_state; end if; end process;。
..end;。
用元件例化語句編寫該電路的頂層VHDL程序
ARCHITECTURE structure OF sample IS SIGANL d,e,f,g: bit; COMPONENT nand3 PORT (a,b,c: IN bit; y: OUT bit); END COMPONENT; COMPONENT and2 PORT (a,b: IN bit; y: OUT bit); END COMPONENT; COMPONENT nor3 PORT (a,b,c: IN bit; y: OUT bit); END COMPONENT;BEGIN u0: nand3 PORT MAP (a => a, b => b, c => c, y => d); u1: and2 PORT MAP (a => a, b => d, y => e); u2: and2 PORT MAP (a => d, b => b, y => f); u3: and2 PORT MAP (a => d, b => c, y => g); u4: nor3 PORT MAP (a => e, b => f, c => g, y => y);END structure;。
